The advance of semiconductor technology not only effectively reduces the size of electronic elements but also obviously decreases the fabrication cost of electronic elements. For many years, planar semiconductor structure is fabricated in limited semiconductor techniques such as etching, ion implantation, wiring, etc. The smallest chip has been as small as 6F2 so far. However, the technical advance in reducing the feature size has been gradually slowed down, and it is hard to further obviously reduce the area occupied by a chip in a wafer. On the other side, the vertical (solid) semiconductor technology is growing mature, wherein the semiconductor structure is vertically grown on a wafer to reduce the area occupied by a transistor, thus the chip size can be reduced to 4F2.
For examples, a US publication No. 20120007171 disclosed “Semiconductor Device Having Vertical Transistor and Buried Bit Line and Method for Fabricating the Same”, and a U.S. Pat. No. 8,120,103 disclosed “Semiconductor Device with Vertical Gate and Method for Fabricating the Same”. In the above-mentioned prior arts, bit lines are fabricated via an ion implantation technique or an etching technique. Next, an oxide layer is deposited on the bit lines to form buried bit lines. Then is undertaken the transistor fabrication process or the DRAM fabrication process.
No matter which method is used to fabricate buried bit lines, trenches and pillars must be fabricated firstly before the succeeding process. The aspect ratio of the trench correlates with the cell size and the number of the transistors accommodated in a unit area. However, the greater the aspect ratio is, the more likely the pillar is to bend or fracture. Therefore, a higher aspect ratio may cause a lower yield. Especially in the 40 nm process, pillars are likely to bend or even collapse because of the high aspect ratio.